Summer 2012 Research Progress Update
Tom Chen, PI
This project is funded by NSF GK-12 program (DGE-0841259) starting from 2009. We are in our 4th year of the program. This project focuses on developing an innovative program for a new generation of scientists in biomedical science and engineering that are trans-disciplinary in their training, better equipped for multilevel communication across ages and fields, and prepared to take leadership roles for scientific inquiry and progress as we move through the 21st century.
The majority of the research work during the 3nd year focused on design of 2nd biosensor chip with support from National Semiconductor Inc. (now TI). All the existing work on the 2nd generation chip will include the electronic functional blocks needed for signal amplification, signal conditioning and processing, and storage. The on-going design activities include completing major functional blocks for the 2nd generation biosensor chip for National Semiconductor’s silicon process. The figure below shows the top level block diagram of the biosensor system.
The initial design of the potentiostat circuit was completed during the 2nd year of the project. One of the key features in the design of the potentiostat is a novel digital assist feature that reduces the offset voltage from 50mV to 2-3mV. This is a very important feature for the 2nd generation biosensor chip. Higher offset voltage can potentially cause mis-identification of chemical elements in solution. Figure 5 shows the silicon layout and the actual silicon die photo of the on-chip potentiostat. The figure below shows the reduction of offset voltage before and after the calibration indicating that the offset voltage was reduced from 50mV to 2-3mV.
Progress was also made in the design of analog-to-digital converter for the 2nd generation biosensor chip. One of the key component in the analog-to-digital converter is the sigma-delta modulator. A 2nd-order sigma-delta modulator architecture was chosen for the 2nd generation biosensor chip. The design focused on achieving low power consumption by using 900mV power supply. The figure below shows the operational amplifier design for the modulator and silicon implementation of the 2nd-order sigma-delta modulator. Figure 8 shows the silicon measurement data of the modulator indicating its full functionality in silicon. Another component inside the analog-to-digital converter is the decimation filter. To achieve low power consumption, bit-serial architecture was chosen. The overall design achieved the lowest power consumption among all existing decimation filter designs published to date. The figure below shows the top level bit-serial decimation filter design and the silicon layout of the filter. The decimation filter is currently being fabricated by National Semiconductors. .